//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Program Data Registers for M8051W/EW
// 
// $Log: m3s012dy.v,v $
// Revision 1.6  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.2  2001/10/31
// First parsable verilog for EW
//
// Revision 1.1.1.1  2001/07/17
// Re-imported E-Warp from Farnham filesystem
//
// Revision 1.5  2000/10/24
// Multiplier rewritten to improve power consumption.
// Code changes for Leonardo (ECN01372).
// Code changes for formal verification tools (ECN01410).
// MOVX @Ri page address controllable from PORT2I if I/O ports ommitted (ECN01387).
//
// Revision 1.4  2000/02/05
// Name change repercussions
//
// Revision 1.3  2000/01/06
// PROGA no longer cleared during idle mode.
// Minor code tidying up.
//
// Revision 1.2  1999/11/30
// More debug changes.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
// Revision 1.1  1999/10/22
// Initial revision
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_defs.v"
`include "m8051w_cfg.v"

// OPCODE is the 8-bit opcode register and is loaded from program memory at the
// at the end of every instruction.  Interrupts and entry to idle mode force a
// hardware-generated opcode to be loaded (LCALL and NOP respectively).
// IMMEDIATE register number 1 is used for 8-bit immediate operands and the
// high byte of a 16-bit operand.
// IMMEDIATE register number 2 is used to store relative addresses
// and the low byte of a 16-bit operand.

module m3s012dy (OPCODE, IMMEDIATE, IMMEDIATE_2, PROGDI, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
                 EXCEPTION, NEXT_STATE_IDLE, INTERNAL_RESET, STATE,
                 LAST_CYC, IMM_CON, INTERNAL_WAIT, DebugNOP, PCLK_EN, CCLK,
		 PCLK);

  output [7:0] OPCODE, IMMEDIATE, IMMEDIATE_2;

  input  [7:0] PROGDI;
  input        EXCEPTION, NEXT_STATE_IDLE, INTERNAL_RESET;
  input  [2:0] STATE;
  input        PCLK_EN;
  input        IMM_CON;
  input        LAST_CYC;
  input        INTERNAL_WAIT;
  input        DebugNOP;
  input        PCLK;
  input        CCLK;

  reg    [7:0] OPCODE, IMMEDIATE, IMMEDIATE_2;

  // Opcode register
  // Normally the register loads program data at the end of each instruction.
  // An exception forces the LCALL opcode to be loaded.
  // Idle, debug and reset modes load the NOP instruction.

  always @(posedge PCLK)
  begin: p_opcode
    if (PCLK_EN && ~INTERNAL_WAIT) begin
      if (INTERNAL_RESET | DebugNOP | NEXT_STATE_IDLE)
        OPCODE <= 8'h00;
      else if (EXCEPTION)
          OPCODE <= 8'h12;
      else if (LAST_CYC) begin
        `ifdef OPC_CORRELATE
          $display("%h", PROGDI);
        `endif
          OPCODE <= PROGDI;
        end
    end
  end

  // Immediate data registers

  always @(posedge CCLK)
  begin: p_immediates
    if ((`C1P1 || `C1P2 && IMM_CON) && ~INTERNAL_WAIT) 
      IMMEDIATE <= PROGDI;
    if (`C1P2 && ~INTERNAL_WAIT) 
      IMMEDIATE_2 <= PROGDI;
  end

endmodule
